riscv: add ISA extension parsing for Zihintntl
authorClément Léger <cleger@rivosinc.com>
Tue, 14 Nov 2023 14:12:48 +0000 (09:12 -0500)
committerPalmer Dabbelt <palmer@rivosinc.com>
Tue, 12 Dec 2023 23:45:09 +0000 (15:45 -0800)
commiteddbfa0d849fa5a315840e8c501962252b48484d
tree80755ce71846d7fbb5363319cfca68523ac73fe8
parentc44714c35ff861d69db9c8bb4ae1347373f817f0
riscv: add ISA extension parsing for Zihintntl

Add parsing for Zihintntl ISA extension[1] that was ratified in commit
0dc91f5 ("Zihintntl is ratified") of riscv-isa-manual[2].

Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view
Link: https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6d
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Link: https://lore.kernel.org/r/20231114141256.126749-13-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/hwcap.h
arch/riscv/kernel/cpufeature.c