clk: aspeed: Add SDIO gate
authorJoel Stanley <joel@jms.id.au>
Wed, 10 Jul 2019 14:10:09 +0000 (23:40 +0930)
committerStephen Boyd <sboyd@kernel.org>
Wed, 7 Aug 2019 21:15:31 +0000 (14:15 -0700)
commitebd5f82d32ade6f864917bf868bfa32f4d3c0486
tree1192220b163e6fe84b154882e856fecaf7e92d5f
parent5f9e832c137075045d15cd6899ab0505cfb2ca4b
clk: aspeed: Add SDIO gate

The clock divisor comes with an enable bit (gate). This was not
implemented as we didn't have access to SD hardware when writing the
driver. Now that we can test it, add the gate as a parent to the
divisor.

There is no reason to expose the gate separately, so users will enable
it by turning on the ASPEED_CLK_SDIO divisor.

Signed-off-by: Joel Stanley <joel@jms.id.au>
[aj: Minor style cleanup]
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lkml.kernel.org/r/20190710141009.20651-1-andrew@aj.id.au
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/clk-aspeed.c