drm/xe/mcr: Add L3BANK steering for DG2
authorLucas De Marchi <lucas.demarchi@intel.com>
Tue, 7 Mar 2023 00:40:27 +0000 (16:40 -0800)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Tue, 19 Dec 2023 23:29:45 +0000 (18:29 -0500)
commite84535d86043af8fc9edcbbeb00f2e47e8ccb130
tree663a9bbe46d9b8ae68c677816c86d0614f2b09f2
parent4b1430f77553ca3e4f9033d4d614b193da233a30
drm/xe/mcr: Add L3BANK steering for DG2

Some register ranges with replication type L3BANK were missing from the
driver table. The following warning was triggering when adding a
workaround touching the register 0xb188:

xe 0000:03:00.0: Did not find MCR register 0xb188 in any MCR steering table

Add the L3BANK ranges according to the spec.

v2:
  - Fix typo in one of the ranges: s/0x00BCFF/0x008CFF/ (Matt Roper)
  - Add termination rule in the init function for L3BANK (Matt Roper)

Bspec: 66534
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/xe_gt_mcr.c