MIPS: Add Loongson-3B support
authorHuacai Chen <chenhc@lemote.com>
Thu, 26 Jun 2014 03:41:30 +0000 (11:41 +0800)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 30 Jul 2014 19:47:00 +0000 (21:47 +0200)
commite7841be50fe2b8751a51a068b8cdcdcb6611e354
treed0ffedc83975c17cfa3357ebcb806a2fa86d3566
parent1ff1ad6bc2c63f219cbc00dcdd35dcf36a7d6fe4
MIPS: Add Loongson-3B support

Loongson-3B is a 8-cores processor. In general it looks like there are
two Loongson-3A integrated in one chip: 8 cores are separated into two
groups (two NUMA node), each node has its own local memory.

Of course there are some differences between one Loongson-3B and two
Loongson-3A. E.g., the base addresses of IPI registers of each node are
not the same; Loongson-3A use ChipConfig register to enable/disable
clock, but Loongson-3B use FreqControl register instead.

There are two revision of Loongson-3B, the first revision is called as
Loongson-3B1000, whose frequency is 1GHz and has a PRid 0x6306, the
second revision is called as Loongson-3B1500, whose frequency is 1.5GHz
and has a PRid 0x6307. Both revisions has a bug that clock cannot be
disabled at runtime, but this will be fixed in future.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7188/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/cpu.h
arch/mips/include/asm/mach-loongson/boot_param.h
arch/mips/include/asm/mach-loongson/loongson.h
arch/mips/kernel/cpu-probe.c
arch/mips/loongson/common/env.c
arch/mips/loongson/loongson-3/irq.c
arch/mips/loongson/loongson-3/smp.c
arch/mips/loongson/loongson-3/smp.h