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(parent: c9e6606) | patch
gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
authorSteven Lee <steven_lee@aspeedtech.com>
Tue, 14 Dec 2021 04:02:38 +0000 (12:02 +0800)
committerBartosz Golaszewski <brgl@bgdev.pl>
Mon, 3 Jan 2022 09:50:12 +0000 (10:50 +0100)
commite5a7431f5a2d6dcff7d516ee9d178a3254b17b87
tree304bf0f03399622a453c459453d6734f96bacf46tree | snapshot
parentc9e6606c7fe92b50a02ce51dda82586ebdf99b48commit | diff
gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler

Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
drivers/gpio/gpio-aspeed-sgpio.c diff | blob | history
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