drm/i915/adlp: Add PIPE_MISC2 programming
authorAnusha Srivatsa <anusha.srivatsa@intel.com>
Wed, 19 May 2021 00:06:24 +0000 (17:06 -0700)
committerLucas De Marchi <lucas.demarchi@intel.com>
Thu, 20 May 2021 06:59:34 +0000 (23:59 -0700)
commite2ca757b6fa415e1aed7bffa240dda918d2301a4
tree0bca0463f0e110130f0ee1ec64a47452229e8bd3
parent414002f1bb8e5a7824ed43373d8de9ba7c658301
drm/i915/adlp: Add PIPE_MISC2 programming

When scalers are enabled, we need to program underrun
bubble counter to 0x50 to avoid Soft Pipe A underruns.
Make sure other bits dont get overwritten.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-17-lucas.demarchi@intel.com
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/i915_reg.h