drm/msm/a6xx: Use barriers while updating HFI Q headers
authorAkhil P Oommen <akhilpo@oss.qualcomm.com>
Fri, 27 Mar 2026 00:13:50 +0000 (05:43 +0530)
committerRob Clark <robin.clark@oss.qualcomm.com>
Tue, 31 Mar 2026 20:47:28 +0000 (13:47 -0700)
commitdc78b35d5ec09d1b0b8a937e6e640d2c5a030915
tree85df23255848524e2c9bfe1ce153298a06b10d9a
parent47cbfe2608314b833ad61a65827d8fb363bc2d2d
drm/msm/a6xx: Use barriers while updating HFI Q headers

To avoid harmful compiler optimizations and IO reordering in the HW, use
barriers and READ/WRITE_ONCE helpers as necessary while accessing the HFI
queue index variables.

Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714653/
Message-ID: <20260327-a8xx-gpu-batch2-v2-1-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
drivers/gpu/drm/msm/adreno/a6xx_hfi.c