drm/amd/display: dce_opp: add DCE6 specific macros,functions
authorMauro Rossi <issor.oruam@gmail.com>
Fri, 10 Jul 2020 18:30:01 +0000 (20:30 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 27 Jul 2020 20:46:28 +0000 (16:46 -0400)
commitd85a1e536ab8cbc9f96f7a0554703887d603c401
treefe727b7e151aa693932d2542a36503db0e3b84fd
parentb91f056fb5e192411635ce9e9e81f9f741ea1f5f
drm/amd/display: dce_opp: add DCE6 specific macros,functions

[Why]
DCE6 has no FMT_TRUNCATE_MODE bit in FMT_BIT_DEPTH_CONTROL register
DCE6 has no FMT_CLAMP_COMPONENT_{R,G,B} registers
DCE6 has no FMT_SUBSAMPLING_{MODE,ORDER} bits in FMT_CONTROL register

[How]
Add DCE6 specific macros definitions for OPP registers and masks
DCE6 OPP macros will avoid buiding errors when using DCE6 headers
Add dce60_set_truncation() w/o FMT_TRUNCATE_MODE bit programming
Add dce60_opp_set_clamping() w/o Format Clamp Component programming
Add dce60_opp_program_fmt() w/o Format Subsampling bits programming
Add dce60_opp_program_bit_depth_reduction() with dce60_set_truncation
Use dce60_opp_program_fmt() in dce60_opp_funcs
Use dce60_opp_program_bit_depth_reduction() in dce60_opp_funcs
Add DCE6 specific dce60_opp_construct

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h