drm/msm/dpu: Sort INTF registers numerically
authorMarijn Suijten <marijn.suijten@somainline.org>
Wed, 26 Apr 2023 22:37:24 +0000 (00:37 +0200)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Mon, 22 May 2023 07:14:17 +0000 (10:14 +0300)
commitd80d7f8912a8cbec16ec55793f4b20fc5e76640f
treeb226668fe335fbb9ab1eeac5dfdd2384d095e905
parentd9388af508436091adc1bce492caebab4586b2dd
drm/msm/dpu: Sort INTF registers numerically

A bunch of registers were appended at the end in e.g. commit
91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
rather than being inserted in a place that maintains numerical sorting:
restore said numerical sorting.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/534213/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-10-27ce1a5ab5c6@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c