dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY
authorAnurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Mon, 29 Jun 2020 12:00:52 +0000 (15:00 +0300)
committerVinod Koul <vkoul@kernel.org>
Mon, 29 Jun 2020 13:18:00 +0000 (18:48 +0530)
commitcea0f76a483d1270ac6f6513964e3e75193dda48
tree77f90f9a47a6cdcd08892d317d2d33110846149a
parentdcbec046507615d7c4b5f6682dc11a1be9a2924c
dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY

Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
Processing System Gigabit Transceiver which provides PHY capabilities to
USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.

Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml [new file with mode: 0644]
include/dt-bindings/phy/phy.h