clk: rockchip: Fix wrong parents for MMC phase clock for rk3328
authorShawn Lin <shawn.lin@rock-chips.com>
Wed, 21 Mar 2018 02:39:18 +0000 (10:39 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Fri, 23 Mar 2018 07:58:19 +0000 (08:58 +0100)
commitce84eca927af24ca27897ba5fee4fbeed443d5fc
treec47d85d0e3e12e04ca4d6d657b5e398050bdd0c7
parent4b0556a441dd37e598887215bc89b49a6ef525b3
clk: rockchip: Fix wrong parents for MMC phase clock for rk3328

commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase if
clock rate is zero") catches some gremlins for clk-rk3328.c that the
parents of MMC phase clock should be clk_{sdmmc, sdio, emmc}, but not
sclk_{sdmmc, sdio, emmc}.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3328.c