projects / linux-2.6-microblaze.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 79ba3fd) | patch
clk: exynos5420: fix cpll clock register offsets
authorChander Kashyap <chander.kashyap@linaro.org>
Thu, 26 Sep 2013 09:06:35 +0000 (14:36 +0530)
committerMike Turquette <mturquette@linaro.org>
Wed, 4 Dec 2013 18:46:45 +0000 (10:46 -0800)
commitcdf64eeeb0d762585e2126f3024458d199c2635d
tree425caea31cd6fd5d0fbdb5af7bae55dc9b6e82cftree
parent79ba3fdafdb5361e5158452ed6b1fca0bc39cbc8commit | diff
clk: exynos5420: fix cpll clock register offsets

Fixes cpll control and lock register offset values for Exynos5420 SoC.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/samsung/clk-exynos5420.c diff | blob | history
MicroBlaze GIT Repository