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MIPS: Octeon: Use lockless interrupt controller operations when possible.
authorDavid Daney <ddaney@caviumnetworks.com>
Tue, 13 Oct 2009 18:26:03 +0000 (11:26 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 2 Nov 2009 11:00:07 +0000 (12:00 +0100)
commitcd847b7857b835f9730d6fc93c3f423fcacc50f7
tree530d31b2ea1c088f5cc6340baf7c2b6a7111e159tree
parentb6b74d5490c3ad88de503e0c5d44e4820b79b678commit | diff
MIPS: Octeon: Use lockless interrupt controller operations when possible.

Some newer Octeon chips have registers that allow lockless operation of
the interrupt controller.  Take advantage of them.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/cavium-octeon/octeon-irq.c diff | blob | history
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