clk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2
authorNikita Yushchenko <nikita.yoush@cogentembedded.com>
Mon, 19 Dec 2016 08:12:09 +0000 (11:12 +0300)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 10 Jan 2017 00:06:41 +0000 (16:06 -0800)
commitc77cbdd11b688fa0d1fbb140473dad4bc47cf5e6
tree23b560a7007fe4bcbd53742b28db46bd3f090b06
parent6205406cf6f282d622f31de25036e6d1ab3a2ff5
clk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2

On vf610, PLL1 and PLL2 have registers to configure fractional part of
frequency multiplier.

This patch adds support for these registers.

This fixes "fast system clock" issue on boards where bootloader sets
fractional multiplier for PLL1.

Suggested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
CC: Chris Healy <cphealy@gmail.com>
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/imx/clk-pllv3.c
drivers/clk/imx/clk-vf610.c
drivers/clk/imx/clk.h