drm/i915: More PVC+DG2 workarounds
authorMatt Roper <matthew.d.roper@intel.com>
Wed, 8 Jun 2022 00:51:08 +0000 (17:51 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Wed, 8 Jun 2022 14:25:03 +0000 (07:25 -0700)
commitc5cb0002d14b6f7aabaf7d67d0515fe70aea7167
tree5eb3703ff328d327c3ec8f5a5a699299e980163f
parent5821a0bbb4c39960975d29d6b58ae290088db0ed
drm/i915: More PVC+DG2 workarounds

A new PVC+DG2 workaround has appeared recently:
 - Wa_16015675438

And a couple existing DG2 workarounds have been extended to PVC:
 - Wa_14015795083
 - Wa_18018781329

Note that Wa_16015675438 asks us to program a register that is in the
0x2xxx range typically associated with the RCS engine, even though PVC
does not have an RCS.  By default the GuC will think we've made a
mistake and throw an exception when it sees this register on a CCS
engine's save/restore list, so we need to pass an extra GuC control flag
to tell it that this is expected and not a problem.

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220608005108.3717895-1-matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_gt_regs.h
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/gt/uc/intel_guc.c
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h