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(parent: 83b4c14) | patch
clk: socfpga: stratix10: fix rate calculation for pll clocks
authorDinh Nguyen <dinguyen@kernel.org>
Tue, 18 Dec 2018 00:06:14 +0000 (18:06 -0600)
committerStephen Boyd <sboyd@kernel.org>
Fri, 11 Jan 2019 23:41:02 +0000 (15:41 -0800)
commitc0a636e4cc2eb39244d23c0417c117be4c96a7fe
tree740172431d775ec750ac2691129d1506d1165a2etree | snapshot
parent83b4c147967b20b9140e38f7b1a79258a8e9fa6fcommit | diff
clk: socfpga: stratix10: fix rate calculation for pll clocks

The main PLL calculation has a mistake. We should be using the
multiplying the VCO frequency, not the parent clock frequency.

Fixes: 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/socfpga/clk-pll-s10.c diff | blob | history
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