net: stmmac: Enable SERDES power up/down sequence
authorVoon Weifeng <weifeng.voon@intel.com>
Mon, 20 Apr 2020 15:42:52 +0000 (23:42 +0800)
committerDavid S. Miller <davem@davemloft.net>
Tue, 21 Apr 2020 22:54:45 +0000 (15:54 -0700)
commitb9663b7ca6ff780555108394c9c1b409f63b99a7
treefe1a33ad9dbbf4cf3feda8a20c64ce1dcdafbafe
parentd7a5502b0bb8bde54973a2ee73e7bd72e6cb195c
net: stmmac: Enable SERDES power up/down sequence

This patch is to enable Intel SERDES power up/down sequence. The SERDES
converts 8/10 bits data to SGMII signal. Below is an example of
HW configuration for SGMII mode. The SERDES is located in the PHY IF
in the diagram below.

<-----------------GBE Controller---------->|<--External PHY chip-->
+----------+         +----+            +---+           +----------+
|   EQoS   | <-GMII->| DW | < ------ > |PHY| <-SGMII-> | External |
|   MAC    |         |xPCS|            |IF |           | PHY      |
+----------+         +----+            +---+           +----------+
       ^               ^                 ^                ^
       |               |                 |                |
       +---------------------MDIO-------------------------+

PHY IF configuration and status registers are accessible through
mdio address 0x15 which is defined as mdio_adhoc_addr. During D0,
The driver will need to power up PHY IF by changing the power state
to P0. Likewise, for D3, the driver sets PHY IF power state to P3.

Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h [new file with mode: 0644]
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
include/linux/stmmac.h