MIPS: KVM: Use tlb_write_random
authorJames Hogan <james.hogan@imgtec.com>
Thu, 29 May 2014 09:16:26 +0000 (10:16 +0100)
committerPaolo Bonzini <pbonzini@redhat.com>
Fri, 30 May 2014 11:00:02 +0000 (13:00 +0200)
commitb5dfc6c10608fdf0c35a747a0a3bf3f6e40a38e1
tree3b9722c836af500a362e73930dbf0f1b21685211
parentfacaaec1a72db90127b71d22e788596cf1991ae1
MIPS: KVM: Use tlb_write_random

When MIPS KVM needs to write a TLB entry for the guest it reads the
CP0_Random register, uses it to generate the CP_Index, and writes the
TLB entry using the TLBWI instruction (tlb_write_indexed()).

However there's an instruction for that, TLBWR (tlb_write_random()) so
use that instead.

This happens to also fix an issue with Ingenic XBurst cores where the
same TLB entry is replaced each time preventing forward progress on
stores due to alternating between TLB load misses for the instruction
fetch and TLB store misses.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: kvm@vger.kernel.org
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: Sanjay Lal <sanjayl@kymasys.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
arch/mips/kvm/kvm_tlb.c