drm/i915: WA for zero memory channel
authorJosé Roberto de Souza <jose.souza@intel.com>
Mon, 24 May 2021 21:48:03 +0000 (14:48 -0700)
committerJosé Roberto de Souza <jose.souza@intel.com>
Tue, 25 May 2021 17:30:26 +0000 (10:30 -0700)
commitb554065cb6fc665bf0dac61cc6e79c73c4e4e21e
tree3aa4c84ce9326ec18dbb8c41359e814a7037dd32
parent8c80332d6735a39f87bb1362c54fa6ede5a844d3
drm/i915: WA for zero memory channel

Commit c457d9cf256e ("drm/i915: Make sure we have enough memory
bandwidth on ICL") assumes that we always have a non-zero
dram_info->channels and uses it as a divisor.
We need num memory channels to be at least 1 for sane bw limits
checking, even when PCode returns 0 or there is a error reading it, so
lets force it to 1 in this case.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210524214805.259692-3-jose.souza@intel.com
drivers/gpu/drm/i915/display/intel_bw.c