drm/i915/fia: FIA registers offset implementation.
authorAnusha Srivatsa <anusha.srivatsa@intel.com>
Thu, 1 Nov 2018 18:55:57 +0000 (11:55 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Fri, 2 Nov 2018 17:43:59 +0000 (10:43 -0700)
commita6576a8d715ae73a7e07bae4cde2c55a066501e6
tree818a63d62c8e3920981bb348a6ebf777b43b42d4
parent0019457e31b2ebf3fab38c20c8097e658daea9b8
drm/i915/fia: FIA registers offset implementation.

The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
from the base - which is the FLexi IO Adaptor. Lets follow the
offset calculation while accessing these registers.

v2:
- Follow spec for numbering - s/0/1(Lucas)
- s/FIA_1/FIA1_BASE (Anusha)

v3:
- Remove register offset defines. (Jani)
- Update comment. (Anusha)

v4: rebase. Remove comment.(Lucas)

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101185557.29585-1-anusha.srivatsa@intel.com
drivers/gpu/drm/i915/i915_reg.h