clk: mediatek: mt8183: Correct parent of CLK_INFRA_SSPM_32K_SELF
authorChen-Yu Tsai <wenst@chromium.org>
Mon, 19 Feb 2024 10:51:24 +0000 (18:51 +0800)
committerStephen Boyd <sboyd@kernel.org>
Thu, 22 Feb 2024 04:55:30 +0000 (20:55 -0800)
commita65083fa663a335008e34f65e184041174a9dc7e
tree43ddabc53ef560d2684761612587c3209b61eefa
parenta32e88f2b20259f5fe4f8eed598bbc85dc4879ed
clk: mediatek: mt8183: Correct parent of CLK_INFRA_SSPM_32K_SELF

CLK_INFRA_SSPM_32K_SELF has the "f_f26m_ck" clock assigned as its parent.
This is inconsistent as the clock is part of a group that are all gates
without dividers, and this makes the kernel think it runs at 26 MHz.

After clarification from MediaTek engineers, the correct parent is
actually the system 32 KHz clock.

Fixes: 1eb8d61ac5c9 ("clk: mediatek: mt8183: Add back SSPM related clocks")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20240219105125.956278-1-wenst@chromium.org
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/mediatek/clk-mt8183.c