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(parent: 97a9b60) | patch
drm/amd/display: Fix incorrect backlight register offset for DCN
authorAric Cyr <aric.cyr@amd.com>
Tue, 28 Jul 2020 01:21:16 +0000 (21:21 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 10 Aug 2020 22:08:36 +0000 (18:08 -0400)
commita49f6727e14caff32419cc3002b9ae9cafb750d7
treed82b0b453629ccfe7b9c03cef2597cf7fedbe086tree | snapshot
parent97a9b60fa3bf29d29d0fc253a98096c02fb8106ecommit | diff
drm/amd/display: Fix incorrect backlight register offset for DCN

[Why]
Typo in backlight refactor inctroduced wrong register offset.

[How]
Change DCE to DCN register map for PWRSEQ_REF_DIV

Cc: stable@vger.kernel.org
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h diff | blob | history
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