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(parent: 002bf2f) | patch
PCI/AER: Use explicit register size for PCI_ERR_CAP
authorIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Tue, 6 Feb 2024 13:57:14 +0000 (15:57 +0200)
committerBjorn Helgaas <bhelgaas@google.com>
Fri, 8 Mar 2024 21:22:46 +0000 (15:22 -0600)
commita37e12bcab22efa05802f87baa0692365ae0ab4d
tree71428563172d75bc5cfe568c824edb4291fbaed7tree
parent002bf2fbc00e5c4b95fb167287e2ae7d1973281ecommit | diff
PCI/AER: Use explicit register size for PCI_ERR_CAP

Use u32 for PCIe AER Capability register variable and name it "aercc"
(Advanced Error Capabilities and Control register, PCIe r6.1 sec 7.8.4.7)
instead of "temp".

Link: https://lore.kernel.org/r/20240206135717.8565-2-ilpo.jarvinen@linux.intel.com
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
[bhelgaas: make subject more specific and match similar previous patches]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
drivers/pci/pcie/aer.c diff | blob | history
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