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clk: renesas: r9a07g044: Add clock and reset entry for SCI1
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Wed, 3 Nov 2021 16:05:37 +0000 (16:05 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 15 Nov 2021 09:47:17 +0000 (10:47 +0100)
commita0d2a2c6736c849463b424a7203f5e0e40949c03
treea6b9d6bf6a217719ea9380695696fe561f5c7849tree | snapshot
parent099ee03271208c880aa33b8833edfacd5010a89acommit | diff
clk: renesas: r9a07g044: Add clock and reset entry for SCI1

Add clock and reset entry for SCI1 interface.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211103160537.32253-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
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