RISC-V: Remove the current perf implementation
authorAtish Patra <atish.patra@wdc.com>
Sat, 19 Feb 2022 00:46:52 +0000 (16:46 -0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Mon, 21 Mar 2022 21:58:12 +0000 (14:58 -0700)
commit9dc6ce80213635cdca611d8b89f74bf010c1a8c6
treee28bfa5958b09599a37ba62abebb9751bccfeae4
parenta9b202606c69312cdaa4db187837820ebf7213b2
RISC-V: Remove the current perf implementation

The current perf implementation in RISC-V is not very useful as it can not
count any events other than cycle/instructions. Moreover, perf record
can not be used or the events can not be started or stopped.

Remove the implementation now for a better platform driver in future
that will implement most of the missing functionality.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/Kconfig
arch/riscv/include/asm/perf_event.h
arch/riscv/kernel/Makefile
arch/riscv/kernel/perf_event.c [deleted file]