drm/i915: fix D_COMP usage on BDW
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Fri, 4 Jul 2014 14:59:58 +0000 (11:59 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 10 Jul 2014 06:27:09 +0000 (08:27 +0200)
commit9ccd5aeb2901aaaabf77f185e2e5ea3a0b577e86
tree201f29314c86977797f72c8c9e844860862d7082
parentf475dadf833691e6173dee9ad05953265f6ffe21
drm/i915: fix D_COMP usage on BDW

On HSW, the D_COMP register can be accessed through the mailbox (read
and write) or through MMIO on a MCHBAR offset (read only). On BDW, the
access should be done through MMIO on another address. So to account
for all these cases, create hsw_read_dcomp() with the correct
implementation for reading, and also fix hsw_write_dcomp() to do the
correct thing on BDW.

With this patch, we can now get back from the PC8+ state on BDW. We
were previously getting a black screen and lots of dmesg errors.
Please notice that the bug only happens when you actually reach the
PC8+ states, not when you only allow it.

Testcase: igt/pm_rpm/rte
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c