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KVM: arm64: Add handling of AArch32 PCMEID{2,3} PMUv3 registers
authorMarc Zyngier <maz@kernel.org>
Thu, 31 Dec 2020 11:39:01 +0000 (11:39 +0000)
committerMarc Zyngier <maz@kernel.org>
Wed, 3 Feb 2021 10:59:26 +0000 (10:59 +0000)
commit99b6a4013fe9331e462ccad351a8ac7a2cb330d6
tree122d2304249369e6f7262973507475d2395a81dbtree | snapshot
parentcb95914685ca6514da9a1592b19255fe679557ebcommit | diff
KVM: arm64: Add handling of AArch32 PCMEID{2,3} PMUv3 registers

Despite advertising support for AArch32 PMUv3p1, we fail to handle
the PMCEID{2,3} registers, which conveniently alias with the top
bits of PMCEID{0,1}_EL1.

Implement these registers with the usual AA32(HI/LO) aliasing
mechanism.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
arch/arm64/kvm/sys_regs.c diff | blob | history
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