drm/amd/display: Use new num clk levels struct for max mclk index
authorDillon Varone <Dillon.Varone@amd.com>
Fri, 11 Nov 2022 19:06:58 +0000 (14:06 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 23 Nov 2022 14:47:14 +0000 (09:47 -0500)
commit982ccdb2b9f91fdb83db06df1939035523c1323c
tree7668b8af1bf40cc24ce8877bff1714c75e24b317
parente3aa827e2ab3ec40ca97a3f846892aac81ce5e3c
drm/amd/display: Use new num clk levels struct for max mclk index

[WHY?]
When calculating watermark and dlg values, the max mclk level index and
associated speed are needed to find the correlated dummy latency value.
Currently the incorrect index is given due to a clock manager refactor.

[HOW?]
Use num_memclk_level from num_entries_per_clk struct for getting the correct max
mem speed.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c