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drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registers
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 12 Dec 2018 21:17:38 +0000 (23:17 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 29 Oct 2020 15:32:20 +0000 (17:32 +0200)
commit96eaeb3dfa40576a7aa195303c538202311cffbc
tree726d74d01730d614f64014fd1e49a9531036a118tree | snapshot
parentbd0cef2a797ac59a103c887b7864b6cf7bd5b512commit | diff
drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registers

Remove the hand rolled array of WM0_PIPE register offsets
and use the standard _MMIO_PIPE3() instead.

v2: Take care of gvt too

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212211738.27770-1-ville.syrjala@linux.intel.com
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
drivers/gpu/drm/i915/gvt/handlers.c diff | blob | history
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
drivers/gpu/drm/i915/intel_pm.c diff | blob | history
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