clk: rockchip: add support for half divider
authorElaine Zhang <zhangqing@rock-chips.com>
Fri, 15 Jun 2018 02:16:50 +0000 (10:16 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Fri, 6 Jul 2018 17:17:57 +0000 (19:17 +0200)
commit956060a52795a060833e8de2d1bb89209e61bed2
tree2cc5d99d9e264bad467efcc7f3458d9875b4743f
parentd409d59f021d4c8c97a2ee29d1cae74773fb36bd
clk: rockchip: add support for half divider

The new Rockchip socs have optional half divider:
The formula is shown as:
freq_out = 2*freq_in / (2*div + 3)
Is this the same for all of new SoCs.

So we use "branch_half_divider" + "COMPOSITE_NOMUX_HALFDIV \
DIV_HALF \ COMPOSITE_HALFDIV \ CMPOSITE_NOGATE_HALFDIV"
to hook that special divider clock-type into our clock-tree.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/Makefile
drivers/clk/rockchip/clk-half-divider.c [new file with mode: 0644]
drivers/clk/rockchip/clk.c
drivers/clk/rockchip/clk.h