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PCI/ASPM: Avoid L0s and L1 on Hi1105 [19e5:1105] Wi-Fi
authorShawn Lin <shawn.lin@rock-chips.com>
Thu, 13 Nov 2025 00:53:18 +0000 (18:53 -0600)
committerBjorn Helgaas <bhelgaas@google.com>
Thu, 13 Nov 2025 12:17:23 +0000 (06:17 -0600)
commit921b3f59b7b00cd7067ab775b0e0ca4eca436c2f
tree07a1917305c4b6a8595434624c7cb7041ffa5e12tree
parent823576c894d73255d35c0d0dabbb6ffecf1f2667commit | diff
PCI/ASPM: Avoid L0s and L1 on Hi1105 [19e5:1105] Wi-Fi

This Wi-Fi advertises the L0s and L1 capabilities but actually it doesn't
support them. This is confirmed by HiSilicon team in actual productization.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/1762916319-139532-1-git-send-email-shawn.lin@rock-chips.com
drivers/pci/quirks.c diff | blob | history
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