drm/i915/guc: Limit number of scratch registers used for H2G
authorMichal Wajdeczko <michal.wajdeczko@intel.com>
Fri, 19 Oct 2018 10:17:24 +0000 (10:17 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Mon, 22 Oct 2018 11:36:49 +0000 (12:36 +0100)
commit9128b10249543200fbd26758beab2e7dd93addfc
tree1a036f839a50d42daae77b530ad865d036021fb1
parentd364dc66e2d5afdd825f79b70d8d81d287b2524a
drm/i915/guc: Limit number of scratch registers used for H2G

We wrongly assumed that GuC is only using last scratch register
for G2H messages, but in fact it is also using register [14] to
report sleep state status. Remove that register from our H2G
send registers pool.

v2: No message from host to GuC uses more than 8 registers and
the GuC FW itself uses an 8-element array to store the H2G message,
so we may reduce our send array to just 8 registers (Daniele)
v3: use explicit define (Daniele)
v4: and explicit comment (Daniele)

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20181019101725.14024-1-michal.wajdeczko@intel.com
drivers/gpu/drm/i915/intel_guc.c
drivers/gpu/drm/i915/intel_guc_fwif.h