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(parent: 5c8fe58) | patch
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
authorSowjanya Komatineni <skomatineni@nvidia.com>
Mon, 21 Dec 2020 21:17:31 +0000 (13:17 -0800)
committerThierry Reding <treding@nvidia.com>
Tue, 26 Jan 2021 23:10:14 +0000 (00:10 +0100)
commit88893986338beebcf5317bda80d43d4f6f7f7c7c
tree6c5575ba3f087bd8e6f9e5afef8c837e3863b3bbtree | snapshot
parent5c8fe583cce542aa0b84adc939ce85293de36e5ecommit | diff
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM

Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.

This patch adds clock ID for this to dt-binding.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
include/dt-bindings/clock/tegra210-car.h diff | blob | history
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