[IA64] 4-level page tables
authorRobin Holt <holt@sgi.com>
Fri, 11 Nov 2005 15:35:43 +0000 (09:35 -0600)
committerTony Luck <tony.luck@intel.com>
Fri, 11 Nov 2005 17:37:29 +0000 (09:37 -0800)
commit837cd0bdf54dd954cd6aa43d250f75ab5db79617
treeef28b91f1ac8c1c9f4244da9be1f994306ef4070
parentd12eb7e11cf30c30f639b2093735af2ac177830b
[IA64] 4-level page tables

This patch introduces 4-level page tables to ia64.  I have run
some benchmarks and found nothing interesting.  Performance has
consistently fallen within the noise range.

It also introduces a config option (setting the default to 3
levels).  The config option prevents having 4 level page
tables with 64k base page size.

Signed-off-by: Robin Holt <holt@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
arch/ia64/Kconfig
arch/ia64/configs/sn2_defconfig
arch/ia64/defconfig
arch/ia64/kernel/ivt.S
include/asm-ia64/page.h
include/asm-ia64/pgalloc.h
include/asm-ia64/pgtable.h