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irqchip/gic-v3: Add quirks for HIP06/07 invalid GICD_TYPER erratum 161010803
authorMarc Zyngier <maz@kernel.org>
Wed, 31 Jul 2019 16:29:33 +0000 (17:29 +0100)
committerMarc Zyngier <maz@kernel.org>
Tue, 20 Aug 2019 09:23:35 +0000 (10:23 +0100)
commit7f2481b39b4c776fb9c03081ffcfe81f4961601c
tree6d0c5f6095ffa9a0672f97af2a67a60d4f0c1b37tree | snapshot
parent25edaed6c7feca8fded25348732c628283304364commit | diff
irqchip/gic-v3: Add quirks for HIP06/07 invalid GICD_TYPER erratum 161010803

It looks like the HIP06/07 SoCs have extra bits in their GICD_TYPER
registers, which confuse the GICv3.1 code (these systems appear to
expose ESPIs while they actually don't).

Detect these systems as early as possible and wipe the fields that
should be RES0 in the register.

Tested-by: John Garry <john.garry@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Documentation/arm64/silicon-errata.rst diff | blob | history
drivers/irqchip/irq-gic-v3.c diff | blob | history
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