Merge patch series "riscv: Allow userspace to directly access perf counters"

Merge patch series "riscv: Allow userspace to directly access perf counters"

Alexandre Ghiti <alexghiti@rivosinc.com> says:

riscv used to allow direct access to cycle/time/instret counters,
bypassing the perf framework, this patchset intends to allow the user to
mmap any counter when accessed through perf.

**Important**: The default mode is now user access through perf only, not
the legacy so some applications will break. However, we introduce a sysctl
perf_user_access like arm64 does, which will allow to switch to the legacy
mode described above.

This version needs openSBI v1.3 *and* a kernel fix that went upstream lately
(https://lore.kernel.org/lkml/20230616114831.3186980-1-maz@kernel.org/T/).

* b4-shazam-merge:
  perf: tests: Adapt mmap-basic.c for riscv
  tools: lib: perf: Implement riscv mmap support
  Documentation: admin-guide: Add riscv sysctl_perf_user_access
  drivers: perf: Implement perf event mmap support in the SBI backend
  drivers: perf: Implement perf event mmap support in the legacy backend
  riscv: Prepare for user-space perf event mmap support
  drivers: perf: Rename riscv pmu sbi driver
  riscv: Make legacy counter enum match the HW numbering
  include: riscv: Fix wrong include guard in riscv_pmu.h
  perf: Fix wrong comment about default event_idx

Link: https://lore.kernel.org/r/20230802080328.1213905-1-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>