clk: sunxi-ng: fix PLL_CPUX adjusting on A33
authorIcenowy Zheng <icenowy@aosc.xyz>
Tue, 13 Dec 2016 15:22:47 +0000 (23:22 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Mon, 2 Jan 2017 21:24:55 +0000 (22:24 +0100)
commit790d929b540661945d1c70652ffb602c5c06ad85
treeb224741b61032a0f7a2810797dd62210adb4773a
parenta43c96427e713bea94e9ef50e8be1f493afc0691
clk: sunxi-ng: fix PLL_CPUX adjusting on A33

When adjusting PLL_CPUX on A33, the PLL is temporarily driven too high,
and the system hangs.

Add a notifier to avoid this situation by temporarily switching to a
known stable 24 MHz oscillator.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu-sun8i-a33.c