dt-bindings: phy: mediatek,mt7621-pci-phy: add clock entries
authorSergio Paracuellos <sergio.paracuellos@gmail.com>
Sat, 8 May 2021 07:09:26 +0000 (09:09 +0200)
committerVinod Koul <vkoul@kernel.org>
Fri, 14 May 2021 10:46:28 +0000 (16:16 +0530)
commit77945a345acfc32b8c1aadf470b55d6a4aa8e01e
tree4e096e50ee7ed96d5cd012343058874cf19f4fef
parent8a981128a81e1cec66c43784f01938953dccac88
dt-bindings: phy: mediatek,mt7621-pci-phy: add clock entries

MT7621 SoC clock driver has already mainlined in
'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")'
Hence update schema with the add of the entries related to
clock. Since until now things were not properly being done
we mark also 'clock' as required in the binding since this
will be now the only way to properly retrieve frequency to be
able to make a correct configuration of the PCIe phy registers.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210508070930.5290-3-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml