drm/i915: Add support for non-power-of-2 FB plane alignment
authorImre Deak <imre.deak@intel.com>
Wed, 25 Dec 2019 17:55:42 +0000 (19:55 +0200)
committerImre Deak <imre.deak@intel.com>
Tue, 7 Jan 2020 11:15:02 +0000 (13:15 +0200)
commit7361bdb26c2ca6714a7a5a3d9dfe3b9db8acf985
tree411ae2cec9810db0eaff1f20d85c81c10e2a7ba8
parent1ee48a61aa57dbdbc3cd2808d8b28df40d938e44
drm/i915: Add support for non-power-of-2 FB plane alignment

At least one framebuffer plane on TGL - the UV plane of YUV semiplanar
FBs - requires a non-power-of-2 alignment, so add support for this. This
new alignment restriction applies only to an offset within an FB, so the
GEM buffer itself containing the FB must still be power-of-2 aligned.
Add a check for this (in practice plane 0, since the plane 0 offset must
be 0).

v2:
- Fix WARN check for alignment=0.
v3:
- Return error for alignment programming bugs. (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191231233756.18753-2-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_display.c