pinctrl: renesas: rzg2l: Fix incorrect PUPD register offset for high pins during...
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 28 Mar 2026 09:05:45 +0000 (09:05 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 27 Apr 2026 09:18:04 +0000 (11:18 +0200)
commit6dba9b7268cc50166bce47608670192fd874e363
tree3c93cf6c06b72e0e8765121f57697a33584eb4ba
parent254f49634ee16a731174d2ae34bc50bd5f45e731
pinctrl: renesas: rzg2l: Fix incorrect PUPD register offset for high pins during suspend/resume

When saving/restoring pull-up/down register state during suspend/resume,
the second PUPD register access was incorrectly using the same base offset
as the first, effectively reading/writing the same register twice instead
of the adjacent one.

Add the correct + 4 byte offset to the second RZG2L_PCTRL_REG_ACCESS32
call so that pupd[1][port] is properly saved and restored from the next
32-bit register in the PUPD register pair, covering pins 4–7 of ports
with 4 or more pins.

Fixes: b2bd65fbb617 ("pinctrl: renesas: rzg2l: Add suspend/resume support for pull up/down")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260328090548.84124-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/pinctrl/renesas/pinctrl-rzg2l.c