soc/tegra: pmc: Ensure that clock rates aren't too high
authorDmitry Osipenko <digetx@gmail.com>
Tue, 2 Mar 2021 12:25:00 +0000 (15:25 +0300)
committerThierry Reding <treding@nvidia.com>
Fri, 26 Mar 2021 12:10:25 +0000 (13:10 +0100)
commit66ee50c6e23432efded0c34ea71428f97cac808a
tree9960e5bb254af32800803d63a7e334816497a2f0
parentc45e66a6b9f40f2e95bc6d97fbf3daa1ebe88c6b
soc/tegra: pmc: Ensure that clock rates aren't too high

Switch all clocks of a power domain to a safe rate which is suitable
for all possible voltages in order to ensure that hardware constraints
aren't violated when power domain state toggles.

Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/soc/tegra/pmc.c