drm/amd/display: Fix vertical interrupt 0 registering issue
authorWayne Lin <Wayne.Lin@amd.com>
Wed, 10 Mar 2021 05:53:24 +0000 (13:53 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 24 Mar 2021 03:36:27 +0000 (23:36 -0400)
commit660d540640c0043b06e12fd59c85cea67925ac49
tree490933e7cab9bb5a7e5992fa27c3beca159e66d0
parent2d78b8d66904b428b446c0ce7115c57fa06dd16b
drm/amd/display: Fix vertical interrupt 0 registering issue

[Why]
Find out that when we are registering vertical interrupt0, we get
DC_IRQ_SOURCE_INVALID when call dc_interrupt_to_irq_source for
DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL.

After analyzing, it's due to the defined value for
DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL is not
(DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL + 1). It's not
incremental sequence.

[How]
Use an array to record all vertical interrupt0 SRCID. While registering
interrupt, use an incremental index to visit the array to get the right
SRCID to register.

Also add error handling to avoid potential pointer problem.

Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c