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(parent: 1abd044) | patch
clk: renesas: r8a779a0: Add SDnH clock to V3U
authorWolfram Sang <wsa+renesas@sang-engineering.com>
Wed, 10 Nov 2021 19:15:52 +0000 (20:15 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 19 Nov 2021 10:27:58 +0000 (11:27 +0100)
commit63494b6f98f26f45e0e7929654dd67d6715cc495
tree41fe9e71c33dc6ae19c4af7f9a3162c96b28638dtree
parent1abd04480866cead7b4129bd03246315b4575334commit | diff
clk: renesas: r8a779a0: Add SDnH clock to V3U

Currently a pass-through clock but we will make it a real divider clock
in the next patches.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-4-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a779a0-cpg-mssr.c diff | blob | history
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