drm/i915: Don't look at unrelated PIPECONF bits for interlaced readout
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 18 Jul 2019 14:50:48 +0000 (17:50 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 20 Sep 2019 18:46:22 +0000 (21:46 +0300)
commit60a02311cc588ae92b4732763650f187c506bc3a
treec2a1177f16b1114e05ccd661c1c24c5f77cd334a
parentcae154fcaefeb1ddab491d6fb651452a93bbf81d
drm/i915: Don't look at unrelated PIPECONF bits for interlaced readout

Since HSW the PIPECONF progressive vs. interlaced selection is done
with just two bits instead of the earlier three. Let's not look at the
extra bit on HSW+. Also gen2 doesn't support interlaced displays at all.

This is actually fine as is currently because the extra bit is mbz (as
are all three bits on gen2). But just to avoid mishaps in the future
if the bits get reused let's only look at what's properly defined.

v2: constify crtc_state

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190718145053.25808-8-ville.syrjala@linux.intel.com
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
drivers/gpu/drm/i915/display/intel_display.c