drm/msm/dpu: fix SSPP register definitions
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Thu, 18 May 2023 22:22:30 +0000 (01:22 +0300)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Sun, 4 Jun 2023 01:44:18 +0000 (04:44 +0300)
commit5f31d7e61ddf5ca8db06455b30d3b3e16d656944
tree051163695c0944d441d602d008a4a10092001373
parent6c93a21d92666b44787ee32d054d48751799aad0
drm/msm/dpu: fix SSPP register definitions

Reorder SSPP register definitions to sort them in the ascending order.
Move register bitfields after the register definitions.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/537903/
Link: https://lore.kernel.org/r/20230518222238.3815293-2-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c