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(parent: 4523a56) | patch
net: stmmac: fix csr_clk can't be zero issue
authorBiao Huang <biao.huang@mediatek.com>
Fri, 24 May 2019 06:26:08 +0000 (14:26 +0800)
committerDavid S. Miller <davem@davemloft.net>
Sat, 25 May 2019 18:02:31 +0000 (11:02 -0700)
commit5e7f7fc538d894b2d9aa41876b8dcf35f5fe11e6
tree9b05f3100a9355e57ce02e1f94ee73e8a65a314dtree | snapshot
parent4523a5611526709ec9b4e2574f1bb7818212651ecommit | diff
net: stmmac: fix csr_clk can't be zero issue

The specific clk_csr value can be zero, and
stmmac_clk is necessary for MDC clock which can be set dynamically.
So, change the condition from plat->clk_csr to plat->stmmac_clk to
fix clk_csr can't be zero issue.

Fixes: cd7201f477b9 ("stmmac: MDC clock dynamically based on the csr clock input")
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c diff | blob | history
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c diff | blob | history
MicroBlaze GIT Repository