RDMA/hns: Fix wrong timer context buffer page size
authorXi Wang <wangxi11@huawei.com>
Fri, 21 May 2021 09:29:53 +0000 (17:29 +0800)
committerJason Gunthorpe <jgg@nvidia.com>
Fri, 28 May 2021 23:13:57 +0000 (20:13 -0300)
commit5e6370d7cc75134b0eb5b15916aab40b628db9e1
tree03c026a0e79af755bf526f83a3bd41d11d36ef22
parent1f704d8cc07269f31daf9bdafe84882ad7596a2c
RDMA/hns: Fix wrong timer context buffer page size

The HEM page size for QPC timer and CQC timer is always 4K and there's no
need to calculate a different size by the hns driver, otherwise the ROCEE
may access an invalid address.

Fixes: 719d13415f59 ("RDMA/hns: Remove duplicated hem page size config code")
Link: https://lore.kernel.org/r/1621589395-2435-4-git-send-email-liweihang@huawei.com
Signed-off-by: Xi Wang <wangxi11@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
drivers/infiniband/hw/hns/hns_roce_hw_v2.c