clk: mmp2: Add support for PLL clock sources
authorLubomir Rintel <lkundrak@v3.sk>
Mon, 9 Mar 2020 19:42:41 +0000 (20:42 +0100)
committerStephen Boyd <sboyd@kernel.org>
Sat, 21 Mar 2020 01:19:31 +0000 (18:19 -0700)
commit5d34d0b32d6c13947b0aa890fc4c68f203491169
treeae0e1acb9a8efb2af010fde05fa44810b534b9f4
parent7de0b8b8b0508af5fed2f2a07e3abb6acac0c466
clk: mmp2: Add support for PLL clock sources

The clk-of-mmp2 driver pretends that the clock outputs from the PLLs are
constant, but in fact they are configurable.

Add logic for obtaining the actual clock rates on MMP2 as well as MMP3.
There is no documentation for either SoC, but the "systemsetting" drivers
from Marvell GPL code dump provide some clue as far as MPMU registers on
MMP2 [1] and MMP3 [2] go.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp2_systemsetting.c
[2] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp3_systemsetting.c

A separate commit will adjust the clk-of-mmp2 driver.

Tested on a MMP3-based Dell Wyse 3020 as well as MMP2-based OLPC
XO-1.75 laptop.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-5-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/mmp/Makefile
drivers/clk/mmp/clk-pll.c [new file with mode: 0644]
drivers/clk/mmp/clk.c
drivers/clk/mmp/clk.h