RISC-V: KVM: fix off-by-one array access in SBI PMU
authorRadim Krčmář <radim.krcmar@oss.qualcomm.com>
Fri, 27 Feb 2026 13:46:16 +0000 (13:46 +0000)
committerAnup Patel <anup@brainfault.org>
Fri, 6 Mar 2026 05:50:30 +0000 (11:20 +0530)
commit5c1bb07871119eae6434c640e5e645a74d54a222
treebba8cb146225175caa4bdfea9dcf53445a0ea1b9
parentc28eb189e481f5dac993d1907710716a9b561890
RISC-V: KVM: fix off-by-one array access in SBI PMU

The indexed array only has RISCV_KVM_MAX_COUNTERS elements.
The out-of-bound access could have been performed by a guest,
but it could only access another guest accessible data.

Fixes: 8f0153ecd3bf ("RISC-V: KVM: Add skeleton support for perf")
Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260227134617.23378-1-radim.krcmar@oss.qualcomm.com
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/kvm/vcpu_pmu.c