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(parent: 7c0043c) | patch
clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
authorGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 18 Sep 2018 08:55:29 +0000 (10:55 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 25 Sep 2018 06:55:56 +0000 (08:55 +0200)
commit5915838b7a4fa6bd6819819de11bfc30a4323ad9
tree103ace63bdd797157399df6228b24d1c0cde750btree | snapshot
parent7c0043c0a48c18fccd43e5cd9f45751316564647commit | diff
clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment

PLL0 runs at 4.8 GHz, i.e. EXTAL x 100.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
drivers/clk/renesas/r8a77990-cpg-mssr.c diff | blob | history
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